Within electronic devices such as information processing devices or between electronic devices, serial transmission has been increasingly performed in order to transfer data signals at high speeds. Typical standards of such high-speed serial transmission are Serial Attached Small Computer System Interface (Serial Attached SCSI) (SAS) and Peripheral Component Interconnect Express (PCI Express, hereinafter, abbreviated as “PCIe”).
Among interface circuits of such high-speed serial transmission, interface circuits that support communication activities at transmission speeds exist. In addition, among the interface circuits that support communication activities at transmission speeds, there exists an interface circuit that determines speeds at the time of communication by performing training of communication at the time of initiating a connection with an opposite-side circuit. In, for example, the SAS standard, a negotiation sequence for determining a communication speed at the time of link-up is specified.
Note that, as a technology related to reconstruction of a PCIe link, there has been proposed a computer system in which slot units are connected to hosts via a link controller and a crosspoint switch so that combination of the hosts and the slots and bandwidths of connection paths are able to be changed.
Such a technology has been disclosed in Japanese Laid-open Patent Publication No. 2007-280237.
In some cases, as a printed-circuit board in which an interface circuit for high-speed serial transmission is implemented or a printed-circuit board in which a transmission path between interface circuits is implemented, a low-cost printed-circuit board having poor transmission quality is used in order to reduce manufacturing costs. In such a case, it is likely that communication between interface circuits is performed at a less-than-desired speed. In a case of performing such training as described above, used for determining a transmission speed at, for example, the time of initiating a connection, it is likely that an interface circuit will fail during link-up at the maximum transmission speed supported by both the interface circuit itself and an opposite side and will initiate communication at a speed lower than the maximum transmission speed.
In one aspect, an object of the present technology is to provide an electronic device, a communication control circuit, and a communication control method that each reduce the chance of reducing communication speed.